/* Definitions of functions for Coincidence Reference Desight */ 
#include "v1495_cr.h"

/* In the functions below  bease address is VME bus address, */
/* not the local address address  */

/* Return status of port A */
epicsInt8  v1495cr_get_a_status( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->a_status_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->a_status_h) );
    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return status of port B */
epicsInt8  v1495cr_get_b_status( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->b_status_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->b_status_h) );
   
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return status of port C */
epicsInt8  v1495cr_get_c_status( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->c_status_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->c_status_h) );
    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return mask of port A */
epicsInt8  v1495cr_get_a_mask( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->a_mask_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->a_mask_h) );
    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return mask of port B */
epicsInt8  v1495cr_get_b_mask( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->b_mask_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->b_mask_h) );
   
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return mask of port C */
epicsInt8  v1495cr_get_c_mask( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->c_mask_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->c_mask_h) );
    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return gate width*/
epicsInt8  v1495cr_get_gate_width( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->gate_width) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return control register for port C */
epicsInt8  v1495cr_get_c_ctrl( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->c_ctrl_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->c_ctrl_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return value of the mode register */
epicsInt8  v1495cr_get_mode( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->mode) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return  value of the scratch register */
epicsInt8  v1495cr_get_scratch( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->scratch) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return control register for Port G */
epicsInt8  v1495cr_get_g_ctrl( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->g_ctrl) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}


/* Return control registers for port D */
epicsInt8  v1495cr_get_d_ctrl( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->d_ctrl_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->d_ctrl_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return data registers for port D */
epicsInt8  v1495cr_get_d_data( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->d_data_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->d_data_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return control registers for port E */
epicsInt8  v1495cr_get_e_ctrl( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->e_ctrl_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->e_ctrl_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return data registers for port E */
epicsInt8  v1495cr_get_e_data( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->e_data_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->e_data_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return control registers for port F */
epicsInt8  v1495cr_get_f_ctrl( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->f_ctrl_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->f_ctrl_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}
/* Return data registers for port F */
epicsInt8  v1495cr_get_f_data( char* baseAddr, epicsUInt32* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Read each 16 bits separately and combine them by hand */ 
    epicsUInt16 val_l = vmeRead16( &(cr_regs->f_data_l) );
    epicsUInt16 val_h = vmeRead16( &(cr_regs->f_data_h) );    
    /* High two bytes get shifted by 16 positions */
    *val = ( ((epicsUInt32)val_h) << 16 ) + (epicsUInt32)val_l;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return revision number */
epicsInt8  v1495cr_get_revision( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->revision) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return PDL control register */
epicsInt8  v1495cr_get_pdl_ctrl( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->pdl_ctrl) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return PDL data register */
epicsInt8  v1495cr_get_pdl_data( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->pdl_data) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return Port D ID Code */
epicsInt8  v1495cr_get_d_idcode( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->d_id_code) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return Port E ID Code */
epicsInt8  v1495cr_get_e_idcode( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->e_id_code) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Return Port F ID Code */
epicsInt8  v1495cr_get_f_idcode( char* baseAddr, epicsUInt16* val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    *val = vmeRead16( &(cr_regs->f_id_code) );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}



/* Change mask for port A */
epicsInt8  v1495cr_set_a_mask( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->a_mask_l), val_l ); 
    vmeWrite16( &(cr_regs->a_mask_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}
/* Change mask for port B */
epicsInt8  v1495cr_set_b_mask( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->b_mask_l), val_l ); 
    vmeWrite16( &(cr_regs->b_mask_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change the mask for port C */
epicsInt8  v1495cr_set_c_mask( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->c_mask_l), val_l ); 
    vmeWrite16( &(cr_regs->c_mask_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change Gate Width */
epicsInt8  v1495cr_set_gate_width( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->gate_width),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change the control register of port C */
epicsInt8  v1495cr_set_c_ctrl( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->c_ctrl_l), val_l ); 
    vmeWrite16( &(cr_regs->c_ctrl_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change mode register */
epicsInt8  v1495cr_set_mode( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->mode),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change value of the scratch register */
epicsInt8  v1495cr_set_scratch( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->scratch),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change control register for Port G */
epicsInt8  v1495cr_set_g_ctrl( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->g_ctrl),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change the control register of port D */
epicsInt8  v1495cr_set_d_ctrl( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->d_ctrl_l), val_l ); 
    vmeWrite16( &(cr_regs->d_ctrl_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Function to set the value of port D */
epicsInt8  v1495cr_set_d_data( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->d_data_l), val_l ); 
    vmeWrite16( &(cr_regs->d_data_h), val_h) ;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}
/* Change the control register of port E */
epicsInt8  v1495cr_set_e_ctrl( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->e_ctrl_l), val_l ); 
    vmeWrite16( &(cr_regs->e_ctrl_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Function to set the value of port E */
epicsInt8  v1495cr_set_e_data( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->e_data_l), val_l ); 
    vmeWrite16( &(cr_regs->e_data_h), val_h) ;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change the control register of port F */
epicsInt8  v1495cr_set_f_ctrl( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->f_ctrl_l), val_l ); 
    vmeWrite16( &(cr_regs->f_ctrl_h), val_h );
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Function to set the value of port F */
epicsInt8  v1495cr_set_f_data( char* baseAddr, epicsUInt32 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
    /* Split the value into 2 16-bits and set each 16 bits separately */ 
    epicsUInt16 val_l = val & LO16_MASK;
    epicsUInt16 val_h = val & HI16_MASK;
    vmeWrite16( &(cr_regs->f_data_l), val_l ); 
    vmeWrite16( &(cr_regs->f_data_h), val_h) ;
    return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change Revision */
epicsInt8  v1495cr_set_revision( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->revision),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change PDL Control register */
epicsInt8  v1495cr_set_pdl_ctrl( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->pdl_ctrl),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}

/* Change PDL data register */
epicsInt8  v1495cr_set_pdl_data( char* baseAddr, epicsUInt16 val ) {
  V1495CR_REGS* cr_regs ;
  if( v1495cr_get_regs( baseAddr, &cr_regs ) == v1495CR_OK ) {
   vmeWrite16( &(cr_regs->pdl_data),  val );
   return v1495CR_OK;
  } 
  return v1495CR_ERROR;
}



/* Return the address registers for CR design after picking it out */ 
/* of the structure for all of the V1495 registers         */  
epicsInt8 v1495cr_get_regs( char* baseAddr, V1495CR_REGS** regs ) {
  V1495_REGS* v1495_regs;
  if( v1495_get_regs( baseAddr, &v1495_regs ) == v1495_OK ) {
    /* Overlay the CR register structure over FPGA ACCESS REGISTERS */
    *regs = (V1495CR_REGS*)v1495_regs->user_fpga_acc;
    return v1495CR_OK;    
  }
  return v1495CR_ERROR;  
}