#ifndef _V1495_CR_REGISTERS_H_ #define _V1495_CR_REGISTERS_H_ /* #include */ /* #include */ /* #include */ /* #include */ /* #include */ #include "jvme.h" #include "v1495.h" #define v1495CR_OK ( 0) #define v1495CR_ERROR (-1) #define LO16_MASK (0x0000FFFF) #define HI16_MASK (0xFFFF0000) /* Register Addresses for the COINCIDENCE REFERENCE DESIGN */ /* for V1495 by CAEN. This needs to be overlayed on top of */ /* the "user_fpga_acc" member of the V1495_REGS structure. */ /* From Technical Information Manual for V1495, Rev. #13 */ typedef volatile struct { epicsUInt16 a_status_l; /* 0x1000 */ epicsUInt16 a_status_h; /* 0x1002 */ epicsUInt16 b_status_l; /* 0x1004 */ epicsUInt16 b_status_h; /* 0x1006 */ epicsUInt16 c_status_l; /* 0x1008 */ epicsUInt16 c_status_h; /* 0x100A */ epicsUInt16 a_mask_l; /* 0x100C */ epicsUInt16 a_mask_h; /* 0x100E */ epicsUInt16 b_mask_l; /* 0x1010 */ epicsUInt16 b_mask_h; /* 0x1012 */ epicsUInt16 c_mask_l; /* 0x1014 */ epicsUInt16 c_mask_h; /* 0x1016 */ epicsUInt16 gate_width; /* 0x1018 */ epicsUInt16 c_ctrl_l; /* 0x101A */ epicsUInt16 c_ctrl_h; /* 0x101C */ epicsUInt16 mode; /* 0x101E */ epicsUInt16 scratch; /* 0x1020 */ epicsUInt16 g_ctrl; /* 0x1022 */ epicsUInt16 d_ctrl_l; /* 0x1024 */ epicsUInt16 d_ctrl_h; /* 0x1026 */ epicsUInt16 d_data_l; /* 0x1028 */ epicsUInt16 d_data_h; /* 0x102A */ epicsUInt16 e_ctrl_l; /* 0x102C */ epicsUInt16 e_ctrl_h; /* 0x102E */ epicsUInt16 e_data_l; /* 0x1030 */ epicsUInt16 e_data_h; /* 0x1032 */ epicsUInt16 f_ctrl_l; /* 0x1034 */ epicsUInt16 f_ctrl_h; /* 0x1036 */ epicsUInt16 f_data_l; /* 0x1038 */ epicsUInt16 f_data_h; /* 0x103A */ epicsUInt16 revision; /* 0x103C */ epicsUInt16 pdl_ctrl; /* 0x103E */ epicsUInt16 pdl_data; /* 0x1040 */ epicsUInt16 d_id_code; /* 0x1042 */ epicsUInt16 e_id_code; /* 0x1044 */ epicsUInt16 f_id_code; /* 0x1046 */ } V1495CR_REGS; /* Basic function declarations */ /* Get functions */ epicsInt8 v1495cr_get_a_status ( char* baseAddr, epicsUInt32* val ); /* Return the status of port A */ epicsInt8 v1495cr_get_b_status ( char* baseAddr, epicsUInt32* val ); /* Return the status of port B */ epicsInt8 v1495cr_get_c_status ( char* baseAddr, epicsUInt32* val ); /* Return the status of port C */ epicsInt8 v1495cr_get_a_mask ( char* baseAddr, epicsUInt32* val ); /* Return the mask of port A */ epicsInt8 v1495cr_get_b_mask ( char* baseAddr, epicsUInt32* val ); /* Return the mask of port B */ epicsInt8 v1495cr_get_c_mask ( char* baseAddr, epicsUInt32* val ); /* Return the mask of port C */ epicsInt8 v1495cr_get_gate_width( char* baseAddr, epicsUInt16* val ); /* Return gate width */ epicsInt8 v1495cr_get_c_ctrl ( char* baseAddr, epicsUInt32* val ); /* Return Port C control register */ epicsInt8 v1495cr_get_mode ( char* baseAddr, epicsUInt16* val ); /* Return Mode register */ epicsInt8 v1495cr_get_scratch ( char* baseAddr, epicsUInt16* val ); /* Return the scratch register */ epicsInt8 v1495cr_get_g_ctrl ( char* baseAddr, epicsUInt16* val ); /* Return Port G control register */ epicsInt8 v1495cr_get_d_ctrl ( char* baseAddr, epicsUInt32* val ); /* Return Port D control register */ epicsInt8 v1495cr_get_d_data ( char* baseAddr, epicsUInt32* val ); /* Return Port D data register */ epicsInt8 v1495cr_get_e_ctrl ( char* baseAddr, epicsUInt32* val ); /* Return Port E control register */ epicsInt8 v1495cr_get_e_data ( char* baseAddr, epicsUInt32* val ); /* Return Port E data register */ epicsInt8 v1495cr_get_f_ctrl ( char* baseAddr, epicsUInt32* val ); /* Return Port F control register */ epicsInt8 v1495cr_get_f_data ( char* baseAddr, epicsUInt32* val ); /* Return Port F data register */ epicsInt8 v1495cr_get_revision ( char* baseAddr, epicsUInt16* val ); /* Return the revision */ epicsInt8 v1495cr_get_pdl_ctrl ( char* baseAddr, epicsUInt16* val ); /* Return PDL control register */ epicsInt8 v1495cr_get_pdl_data ( char* baseAddr, epicsUInt16* val ); /* Return PDL data register */ epicsInt8 v1495cr_get_d_idcode ( char* baseAddr, epicsUInt16* val ); /* Return Port D ID Code */ epicsInt8 v1495cr_get_e_idcode ( char* baseAddr, epicsUInt16* val ); /* Return Port E ID Code */ epicsInt8 v1495cr_get_f_idcode ( char* baseAddr, epicsUInt16* val ); /* Return Port F ID Code */ /* Set functions */ epicsInt8 v1495cr_set_c_status ( char* baseAddr, epicsUInt32 val ); /* Set the status of port C */ epicsInt8 v1495cr_set_a_mask ( char* baseAddr, epicsUInt32 val ); /* Set the mask of port A */ epicsInt8 v1495cr_set_b_mask ( char* baseAddr, epicsUInt32 val ); /* Set the mask of port B */ epicsInt8 v1495cr_set_c_mask ( char* baseAddr, epicsUInt32 val ); /* Set the mask of port C */ epicsInt8 v1495cr_set_gate_width( char* baseAddr, epicsUInt16 val ); /* Set gate width */ epicsInt8 v1495cr_set_c_ctrl ( char* baseAddr, epicsUInt32 val ); /* Set Port C control register */ epicsInt8 v1495cr_set_mode ( char* baseAddr, epicsUInt16 val ); /* Set Mode register */ epicsInt8 v1495cr_set_scratch ( char* baseAddr, epicsUInt16 val ); /* Set the scratch register value */ epicsInt8 v1495cr_set_g_ctrl ( char* baseAddr, epicsUInt16 val ); /* Set Port G control register */ epicsInt8 v1495cr_set_d_ctrl ( char* baseAddr, epicsUInt32 val ); /* Set Port D control register */ epicsInt8 v1495cr_set_d_data ( char* baseAddr, epicsUInt32 val ); /* Set Port D data register */ epicsInt8 v1495cr_set_e_ctrl ( char* baseAddr, epicsUInt32 val ); /* Set Port E control register */ epicsInt8 v1495cr_set_e_data ( char* baseAddr, epicsUInt32 val ); /* Set Port E data register */ epicsInt8 v1495cr_set_f_ctrl ( char* baseAddr, epicsUInt32 val ); /* Set Port F control register */ epicsInt8 v1495cr_set_f_data ( char* baseAddr, epicsUInt32 val ); /* Set Port F data register */ epicsInt8 v1495cr_set_revision ( char* baseAddr, epicsUInt16 val ); /* Set Rrevision register */ epicsInt8 v1495cr_set_pdl_ctrl ( char* baseAddr, epicsUInt16 val ); /* Set PDL control register */ epicsInt8 v1495cr_set_pdl_data ( char* baseAddr, epicsUInt16 val ); /* Set PDL data register */ epicsInt8 v1495cr_get_regs( char* baseAddr, V1495CR_REGS** regs ); #endif