/************************************************************************* * * vme_block1.c - TI-based triggered readout of VETROC. * Ideally we'd use vetrocReadBlock instead of * vetrocReadFIFO. * * */ #define MAX_EVENT_LENGTH 5*10240 /* in Bytes */ #define MAX_EVENT_POOL 400 /* in number of events */ #define BLOCKLEVEL 1 /* in events */ #define BUFFERLEVEL 1 /* in number of blocks */ #define MAXVETROCDATA 10000 #define VETROC_SLOT 3 /* Define Interrupt source and address */ #define TI_MASTER #define TI_READOUT TI_READOUT_EXT_POLL /* Poll for available data, external triggers */ #define TI_ADDR (21<<19) /* GEO slot 4 */ /* Decision on whether or not to readout the TI for each block - Comment out to disable readout */ #define TI_DATA_READOUT #define FIBER_LATENCY_OFFSET 0x4A /* measured longest fiber length */ #include "dmaBankTools.h" #include "tiprimary_list.c" /* source required for CODA */ #include "SIS3800.h" /* scaler library */ #include "vetrocLib.h" /* VETROC library */ #include "gtpLib.h" /* GTP library */ #define SCAL_ADDR 0xab2000 int use_scaler=0; static struct SIS3800CSREG *pScaler; static unsigned int vetrocSlotMask=0; int nvetroc=0; /* Redefine tsCrate according to TI_MASTER or TI_SLAVE */ #ifdef TI_SLAVE int tsCrate=0; #else #ifdef TI_MASTER int tsCrate=1; #endif #endif /* function prototype */ void rocTrigger(int arg); /**************************************** * DOWNLOAD *****************Front Panel TRG***********************/ void rocDownload() { int res, mode, iflag; unsigned long laddr; /* Set up DMA */ vmeDmaConfig(2,5,1); /***************** * TI SETUP *****************/ int overall_offset=0x80; #ifndef TI_DATA_READOUT /* Disable data readout */ tiDisableDataReadout(); /* Disable A32... where that data would have been stored on the TI */ tiDisableA32(); #endif /* Set crate ID */ tiSetCrateID(0x01); /* ROC 1 */ /* tiSetTriggerSource(TI_TRIGGER_TSINPUTS); */ tiSetTriggerSource(TI_TRIGGER_FPTRG); //tiSetTriggerPulse(1, 700, 5); /* Set needed TS input bits */ tiEnableTSInput( TI_TSINPUT_1 ); /* Load the trigger table that associates pins 21/22 | 23/24 | 25/26 : trigger1 pins 29/30 | 31/32 | 33/34 : trigger2 */ tiLoadTriggerTable(0); tiSetTriggerHoldoff(4,4,1); /* /\* Set the sync delay width to 0x40*32 = 2.048us *\/ */ tiSetSyncDelayWidth(0x54, 0x40, 1); /* Set the busy source to non-default value (no Switch Slot B busy) */ tiSetBusySource(TI_BUSY_LOOPBACK,1); /* tiSetFiberDelay(10,0xcf); */ printf("Block level = %d\n",BLOCKLEVEL); tiSetBlockLevel(BLOCKLEVEL); tiSetBlockBufferLevel(BUFFERLEVEL); tiSetBlockLimit(0); tiSetPrescale(0); tiStatus(0); /* scalers */ pScaler = 0; if (use_scaler) { printf("Setting up pScaler - address 0x%x\n",SCAL_ADDR); res = vmeBusToLocalAdrs(0x39,(char *)SCAL_ADDR,(char **)&laddr); if (res != 0) { printf("Scaler: ERROR: vmeBusToLocalAdrs: scaler at offset 0x%x address= 0x%x\n",SCAL_ADDR,laddr); } else { pScaler = (struct SIS3800CSREG *)laddr; vmeWrite32(&pScaler->reset,1); vmeWrite32(&pScaler->csr,0x7000fd00); vmeWrite32(&pScaler->enclk,1); mode = 1; vmeWrite32(&pScaler->csr,0x00000C00); vmeWrite32(&pScaler->csr,mode<<2); vmeWrite32(&pScaler->clear,1); printf("Scaler: Have setup and cleared \n"); } } /* for VETROC */ vetrocSlotMask=0; vetrocSlotMask |= (1<0) break; } if (debug) { printf("gbready = %d read_stat = %d \n",gbready, read_stat); printf("vetrocSlotMask = %d \n",vetrocSlotMask); } if(read_stat>0) { /* read the data here */ *dma_dabufp++ = LSWAP(0xb0b0b0b4); nwords = vetrocReadBlock(VETROC_SLOT,dma_dabufp, MAXVETROCDATA, 1); //printf("vetrocReadBlock returns nwords = %d \n", nwords); // added debug statement for single-shot testing -- REM -- 2017-05-09 *dma_dabufp = LSWAP(nwords); dma_dabufp += nwords; //empty histos no 0xffffffff //dma_dabufp += nwords; //empty histos one 0xffffffff //*dma_dabufp++ = LSWAP(nwords); //dma_dabufp += nwords; //histos look good two 0xffffffff *dma_dabufp++ = LSWAP(read_stat); //dma_dabufp += nwords; //histos look good three 0xffffffff *dma_dabufp++ = LSWAP(vetrocDready(VETROC_SLOT,1)); //dma_dabufp += nwords; //histos look good four 0xffffffff *dma_dabufp++ = LSWAP(vetrocDready(VETROC_SLOT,0)); //dma_dabufp += nwords; //histos look good 5 0xffffffff } else { printf("ERROR: Data not ready in event %d\n",tiGetIntCount()); *dma_dabufp++ = LSWAP(0xda000bad); } BANKCLOSE; BANKOPEN(5,BT_UI4,0); *dma_dabufp++ = LSWAP(0xfb1b1b1b); mycount++; *dma_dabufp++ = LSWAP(mycount); *dma_dabufp++ = LSWAP(tiGetIntCount()); busytime = tiGetBusyTime(); livetime = tiGetLiveTime(); *dma_dabufp++ = LSWAP(busytime); *dma_dabufp++ = LSWAP(livetime); if (use_scaler && pScaler) { *dma_dabufp++ = LSWAP(0xb0b0b444); *dma_dabufp++ = LSWAP(vmeRead32(&pScaler->readCounter[8])); *dma_dabufp++ = LSWAP(vmeRead32(&pScaler->readCounter[9])); *dma_dabufp++ = LSWAP(vmeRead32(&pScaler->readCounter[10])); } BANKCLOSE; // BLOCKCLOSE; tiSetOutputPort(0,0,0,0); // blkcnt = vetrocDready(VETROC_SLOT,1); // evtcnt = vetrocDready(VETROC_SLOT,0); // Tried this; it does not work // if (blkcnt < 50 || evtcnt < 1000) { // vetrocWriteCnt(VETROC_SLOT, defblk, defevt); // } } void rocCleanup() { int islot=0; printf("%s: Reset all FADCs\n",__FUNCTION__); }