From braydo@jlab.org Tue Apr 28 09:59:19 2015
Date: Tue, 28 Apr 2015 09:59:18 -0400 (EDT)
From: Benjamin Raydo <braydo@jlab.org>
To: Alexandre Camsonne <camsonne@jlab.org>, Robert Michaels <rom@jlab.org>
Cc: jgu <jgu@jlab.org>, C. Cuevas <cuevas@jlab.org>
Subject: VETROC ready for testing

Hi Alexandre and Bob,

I have the firmware ready for the VETROC board/application.

In summary of what this firmware does:
 - 128 channel TDC with 1ns resolution rising/falling edge detection (channels are maskable)
 - programmable window size and programmable offset: up to 8us
 - onboard buffering holds around 500,000 TDC hits (intended for holding many events)
 - 32bit scaler for each TDC channel (counts rising edges)
 - programmable trigger pulse width (8ns to 2048ns)
 - all 128 trigger pulses are sampled every 32ns and sent serially over VXS connection to CTP (no firmware exists on CTP to handle this at the moment)
 - supports 2eSST 200MB/s VME transfer and well as several other block transfer modes (BLT, MBLT, 2eVME)

In the attachments I've included example libraries (vetrocLib.c/h) that I've used with CODA in a Hall B setup to do initial testing of the VETROC (I've demonstrated I can trigger the board and readout a few TDC channels running the full CODA DAQ).

VETROC_EventFormat.pdf details what you readout from the board. It basically uses the same structure as the FADC250 (so header/trailer/trigger time should look familiar), but there is a type for the TDC hit format.

vetroc_rol_notes.txt provides some notes/example of what kind you need to add to the ROL to use this board...The Hall B ROL is bloated with so much stuff that I don't think it's a good example, but if you want to look at it I can forward it to you.

I currently have this board running in a setup in the EEL building and can hand off the board whenever you're ready to try it out. What you'll need is a TI and SD card (and the TI needs to be configured to send a 125MHz clock to the backplane).

Thanks,
Ben

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