#
# fadc125 config file - example
#
# this file contains settings for
# fADC125 - JLAB VXS Flash ADC 12-bit 125 Msps 72 ch
#
# format:
# ~~~~~~~
# CRATE             roccdc2   <- ROC name,
# FADC125_ALLSLOTS            <- just keyword - all settings after this line will be implemented
#                                                for all slots, till FADC250_SLOTS will be met
# FADC125_SLOTS     3 4 5 ... <- list of slot numbers to be used
#
# FADC125_FW_REV     0x00010101     <- main firmware revision 
# FADC125_FE_REV     0x00010101     <- front end firmware revision
# FADC125_PROC_REV   0x00010101     <-  Processing Revision 
#
# FADC125_MODE      1   <- process mode: 1-4  (0x10C Bits:2-0)
# FADC125_W_OFFSET  500  <- number of sample back from trigger point.
# FADC125_W_WIDTH   160  <- number of ADC sample to include in trigger window
# the following  parameters do not make much sense for the F125 yet
# FADC125_NSB       3   <- number of sample before trigger point to include in data processing. 
# FADC125_NSA       6   <- number of sample after trigger point to include in data processing.
# FADC125_NPEAK     1   <- number of Pulses in Mode 2 and 3.  (0x10C Bits:6-5)
#
# FADC125_DAC_DEF   0x8000 <- default DAC values if not found in DB
# FADC125_THR_DEF   200    <- defaylt sparsification value ADC counts above pedestal



CRATE 	 roccdc4

#FADC125_ALLSLOTS

###########################
FADC125_SLOTS	3 4 5 6 7 8 9 10 13 14 15 16 17 
###########################

FADC125_F_REV  0x0101  
FADC125_B_REV  0x0001
FADC125_TYPE   0x0001

FADC125_MODE      1
FADC125_W_OFFSET  500
FADC125_W_WIDTH   160
FADC125_NSB       3
FADC125_NSA       6
FADC125_NPEAK     1

FADC125_DAC_DEF   0x8000
FADC125_THR_DEF   200