# # fadc250 config file - example # # this file contains settings for # fADC250 - JLAB VXS Flash ADC 12-bit 250 Msps 16 ch # # format: # ~~~~~~~ # CRATE rocbcal1 <- ROC name, crate name, usually IP name # FADC250_ALLSLOTS <- just keyword - all settings after this line will be implemented # for all slots, till FADC250_SLOTS will be met # FADC250_SLOTS 3 8 15 <- slot_numbers - in which next settings will be implemented # till file ends or next FADC250_SLOTS will be met # # FADC250_F_REV 0x0216 <- firmware revision (0x0 Bits:7-0) # FADC250_B_REV 0x0908 <- board revision (0x0 Bits:15-8) # FADC250_ID 0xfadc <- board type (0x0 Bits:31-16) # # FADC250_MODE 1 <- process mode: 1-4 (0x10C Bits:2-0) # FADC250_W_OFFSET 50 <- number of sample back from trigger point. (0x120) # (in Manual it is PL=Trigger_Window(ns) * 250MHz) # FADC250_W_WIDTH 49 <- number of ADC sample to include in trigger window. (0x11C) # (in M: PTW=Trigger_Window(ns) * 250MHz, minimum is 6) # FADC250_NSB 3 <- number of sample before trigger point to include in data processing. (0x124) # This include the trigger Point. (minimum is 2 in all mode) # FADC250_NSA 6 <- number of sample after trigger point to include in data processing. (0x128) # Minimum is (6 in mode 2) and ( 3 in mode 0 and 1). # Number of sample report is 1 more for odd and 2 more for even NSA number. # FADC250_NPEAK 1 <- number of Pulses in Mode 2 and 3. (0x10C Bits:6-5) # # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - channels ## # FADC250_ADC_MASK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 <- channel enable mask (0x110) # FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- trigger enable mask # (channel includes in global trigger, if bit set to 1) # FADC250_TET 110 <- board Trigger Energy Threshold (TET), same for all 16 channels # FADC250_CH_TET 0 110 <- channel# and TET_value for this channel # FADC250_ALLCH_TET 111 222 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <- 16 TETs (0x12C - 0x148) # # FADC250_DAC 3300 <- board DAC, one and the same for all 16 channels # FADC250_CH_DAC 0 3300 <- channel# and DAC_value for this channel # FADC250_ALLCH_DAC 3300 3280 3310 3280 3310 3280 3310 3280 3300 3280 3300 3280 3310 3280 3310 3280 <- 16 DACs # # FADC250_PED 210 <- board Pedestals, same for all channels # FADC250_CH_PED 0 210 <- channel# and Pedestal_value for this channel # FADC250_ALLCH_PED 210 220 210 215 215 220 220 210 210 215 215 220 220 210 215 220 <- 16 PEDs CRATE rocfcal4 #FADC250_ALLSLOTS ############################ FADC250_SLOTS 3 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3348 3386 3367 3351 3360 3368 3361 3385 3349 3371 3360 3371 3366 3373 3380 3364 FADC250_PED 10 ############################ FADC250_SLOTS 4 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3349 3370 3374 3399 3375 3374 3397 3396 3408 3399 3394 3376 3375 3380 3394 3414 FADC250_PED 10 ############################ FADC250_SLOTS 5 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3359 3364 3353 3359 3373 3386 3380 3370 3363 3354 3368 3374 3352 3351 3357 3343 FADC250_PED 10 ############################ FADC250_SLOTS 6 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3389 3374 3367 3399 3399 3403 3366 3382 3373 3389 3394 3375 3402 3397 3366 3389 FADC250_PED 10 ############################ FADC250_SLOTS 7 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3380 3371 3334 3361 3374 3377 3360 3358 3406 3383 3370 3382 3362 3367 3351 3356 FADC250_PED 10 ############################ FADC250_SLOTS 8 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3344 3354 3363 3364 3363 3372 3384 3371 3371 3391 3368 3368 3386 3364 3366 3367 FADC250_PED 10 ############################ FADC250_SLOTS 9 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3337 3364 3359 3359 3347 3353 3337 3351 3347 3361 3362 3374 3355 3354 3327 3370 FADC250_PED 10 ############################ FADC250_SLOTS 10 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3364 3385 3363 3356 3360 3378 3368 3384 3361 3368 3373 3361 3380 3405 3384 3348 FADC250_PED 10 ############################ FADC250_SLOTS 13 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3369 3364 3352 3358 3374 3365 3376 3373 3381 3343 3372 3380 3361 3340 3365 3365 FADC250_PED 10 ############################ FADC250_SLOTS 14 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3368 3383 3368 3357 3350 3397 3361 3365 3388 3368 3359 3350 3393 3386 3356 3331 FADC250_PED 10 ############################ FADC250_SLOTS 15 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3340 3372 3355 3360 3365 3366 3350 3367 3342 3372 3366 3365 3375 3371 3375 3364 FADC250_PED 10 ############################ FADC250_SLOTS 16 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3363 3351 3361 3386 3382 3374 3371 3386 3392 3358 3364 3361 3381 3376 3368 3363 FADC250_PED 10 ############################ FADC250_SLOTS 17 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3369 3367 3379 3373 3372 3403 3351 3368 3389 3380 3394 3374 3385 3372 3389 3363 FADC250_PED 10 ############################ FADC250_SLOTS 18 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3374 3381 3370 3384 3399 3392 3395 3395 3394 3390 3381 3382 3363 3381 3366 3388 FADC250_PED 10