# # fadc250 config file - example # # this file contains settings for # fADC250 - JLAB VXS Flash ADC 12-bit 250 Msps 16 ch # # format: # ~~~~~~~ # CRATE rocbcal1 <- ROC name, crate name, usually IP name # FADC250_ALLSLOTS <- just keyword - all settings after this line will be implemented # for all slots, till FADC250_SLOTS will be met # FADC250_SLOTS 3 8 15 <- slot_numbers - in which next settings will be implemented # till file ends or next FADC250_SLOTS will be met # # FADC250_F_REV 0x0216 <- firmware revision (0x0 Bits:7-0) # FADC250_B_REV 0x0908 <- board revision (0x0 Bits:15-8) # FADC250_ID 0xfadc <- board type (0x0 Bits:31-16) # # FADC250_MODE 1 <- process mode: 1-4 (0x10C Bits:2-0) # FADC250_W_OFFSET 50 <- number of sample back from trigger point. (0x120) # (in Manual it is PL=Trigger_Window(ns) * 250MHz) # FADC250_W_WIDTH 49 <- number of ADC sample to include in trigger window. (0x11C) # (in M: PTW=Trigger_Window(ns) * 250MHz, minimum is 6) # FADC250_NSB 3 <- number of sample before trigger point to include in data processing. (0x124) # This include the trigger Point. (minimum is 2 in all mode) # FADC250_NSA 6 <- number of sample after trigger point to include in data processing. (0x128) # Minimum is (6 in mode 2) and ( 3 in mode 0 and 1). # Number of sample report is 1 more for odd and 2 more for even NSA number. # FADC250_NPEAK 1 <- number of Pulses in Mode 2 and 3. (0x10C Bits:6-5) # # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - channels ## # FADC250_ADC_MASK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 <- channel enable mask (0x110) # FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- trigger enable mask # (channel includes in global trigger, if bit set to 1) # FADC250_TET 110 <- board Trigger Energy Threshold (TET), same for all 16 channels # FADC250_CH_TET 0 110 <- channel# and TET_value for this channel # FADC250_ALLCH_TET 111 222 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <- 16 TETs (0x12C - 0x148) # # FADC250_DAC 3300 <- board DAC, one and the same for all 16 channels # FADC250_CH_DAC 0 3300 <- channel# and DAC_value for this channel # FADC250_ALLCH_DAC 3300 3280 3310 3280 3310 3280 3310 3280 3300 3280 3300 3280 3310 3280 3310 3280 <- 16 DACs # # FADC250_PED 210 <- board Pedestals, same for all channels # FADC250_CH_PED 0 210 <- channel# and Pedestal_value for this channel # FADC250_ALLCH_PED 210 220 210 215 215 220 220 210 210 215 215 220 220 210 215 220 <- 16 PEDs CRATE rocfcal6 #FADC250_ALLSLOTS ############################ FADC250_SLOTS 3 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3360 3372 3360 3369 3382 3390 3389 3368 3376 3382 3371 3361 3394 3387 3389 3365 FADC250_PED 10 ############################ FADC250_SLOTS 4 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3383 3365 3382 3392 3403 3382 3377 3396 3381 3368 3380 3356 3388 3379 3380 3368 FADC250_PED 10 ############################ FADC250_SLOTS 5 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3369 3388 3379 3353 3376 3363 3381 3389 3387 3382 3367 3378 3359 3378 3363 3374 FADC250_PED 10 ############################ FADC250_SLOTS 6 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3339 3352 3362 3347 3363 3367 3380 3359 3350 3363 3355 3353 3409 3339 3367 3355 FADC250_PED 10 ############################ FADC250_SLOTS 7 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3358 3354 3353 3358 3387 3365 3370 3359 3379 3394 3362 3358 3354 3367 3372 3368 FADC250_PED 10 ############################ FADC250_SLOTS 8 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3367 3329 3366 3354 3362 3391 3391 3366 3357 3373 3361 3394 3379 3368 3350 3340 FADC250_PED 10 ############################ FADC250_SLOTS 9 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3353 3366 3358 3354 3352 3400 3389 3358 3363 3385 3371 3374 3372 3332 3334 3366 FADC250_PED 10 ############################ FADC250_SLOTS 10 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3373 3346 3371 3363 3412 3372 3385 3393 3359 3360 3385 3395 3387 3402 3357 3374 FADC250_PED 10 ############################ FADC250_SLOTS 13 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3356 3376 3349 3348 3363 3366 3372 3384 3372 3385 3363 3358 3385 3363 3355 3359 FADC250_PED 10 ############################ FADC250_SLOTS 14 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3382 3376 3394 3391 3390 3356 3399 3401 3378 3357 3353 3369 3368 3374 3382 3356 FADC250_PED 10 ############################ FADC250_SLOTS 15 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3349 3388 3357 3353 3384 3361 3380 3379 3385 3388 3377 3359 3377 3370 3366 3357 FADC250_PED 10 ############################ FADC250_SLOTS 16 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3368 3381 3350 3355 3376 3352 3376 3346 3365 3366 3362 3397 3372 3343 3372 3366 FADC250_PED 10 ############################ FADC250_SLOTS 17 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3330 3367 3346 3341 3359 3362 3351 3368 3346 3369 3343 3372 3372 3347 3344 3335 FADC250_PED 10 ############################ FADC250_SLOTS 18 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3371 3384 3362 3383 3394 3373 3386 3390 3369 3402 3377 3374 3387 3362 3377 3383 FADC250_PED 10