# # fadc250 config file - example # # this file contains settings for # fADC250 - JLAB VXS Flash ADC 12-bit 250 Msps 16 ch # # format: # ~~~~~~~ # CRATE rocbcal1 <- ROC name, crate name, usually IP name # FADC250_ALLSLOTS <- just keyword - all settings after this line will be implemented # for all slots, till FADC250_SLOTS will be met # FADC250_SLOTS 3 8 15 <- slot_numbers - in which next settings will be implemented # till file ends or next FADC250_SLOTS will be met # # FADC250_F_REV 0x0216 <- firmware revision (0x0 Bits:7-0) # FADC250_B_REV 0x0908 <- board revision (0x0 Bits:15-8) # FADC250_ID 0xfadc <- board type (0x0 Bits:31-16) # # FADC250_MODE 1 <- process mode: 1-4 (0x10C Bits:2-0) # FADC250_W_OFFSET 50 <- number of sample back from trigger point. (0x120) # (in Manual it is PL=Trigger_Window(ns) * 250MHz) # FADC250_W_WIDTH 49 <- number of ADC sample to include in trigger window. (0x11C) # (in M: PTW=Trigger_Window(ns) * 250MHz, minimum is 6) # FADC250_NSB 3 <- number of sample before trigger point to include in data processing. (0x124) # This include the trigger Point. (minimum is 2 in all mode) # FADC250_NSA 6 <- number of sample after trigger point to include in data processing. (0x128) # Minimum is (6 in mode 2) and ( 3 in mode 0 and 1). # Number of sample report is 1 more for odd and 2 more for even NSA number. # FADC250_NPEAK 1 <- number of Pulses in Mode 2 and 3. (0x10C Bits:6-5) # # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - channels ## # FADC250_ADC_MASK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 <- channel enable mask (0x110) # FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- trigger enable mask # (channel includes in global trigger, if bit set to 1) # FADC250_TET 110 <- board Trigger Energy Threshold (TET), same for all 16 channels # FADC250_CH_TET 0 110 <- channel# and TET_value for this channel # FADC250_ALLCH_TET 111 222 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <- 16 TETs (0x12C - 0x148) # # FADC250_DAC 3300 <- board DAC, one and the same for all 16 channels # FADC250_CH_DAC 0 3300 <- channel# and DAC_value for this channel # FADC250_ALLCH_DAC 3300 3280 3310 3280 3310 3280 3310 3280 3300 3280 3300 3280 3310 3280 3310 3280 <- 16 DACs # # FADC250_PED 210 <- board Pedestals, same for all channels # FADC250_CH_PED 0 210 <- channel# and Pedestal_value for this channel # FADC250_ALLCH_PED 210 220 210 215 215 220 220 210 210 215 215 220 220 210 215 220 <- 16 PEDs CRATE rocfcal9 #FADC250_ALLSLOTS ############################ FADC250_SLOTS 3 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3401 3357 3380 3356 3369 3365 3368 3400 3352 3394 3349 3369 3404 3378 3369 3390 FADC250_PED 10 ############################ FADC250_SLOTS 4 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3358 3366 3388 3339 3368 3395 3374 3347 3360 3373 3380 3368 3367 3371 3366 3361 FADC250_PED 10 ############################ FADC250_SLOTS 5 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3359 3359 3366 3375 3365 3378 3358 3346 3372 3359 3343 3363 3372 3364 3356 3355 FADC250_PED 10 ############################ FADC250_SLOTS 6 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3378 3378 3392 3366 3375 3385 3375 3344 3369 3389 3371 3346 3368 3359 3387 3408 FADC250_PED 10 ############################ FADC250_SLOTS 7 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3376 3357 3380 3331 3377 3360 3358 3368 3361 3371 3353 3336 3338 3354 3364 3350 FADC250_PED 10 ############################ FADC250_SLOTS 8 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3355 3384 3362 3375 3358 3387 3380 3371 3374 3385 3374 3368 3352 3384 3372 3379 FADC250_PED 10 ############################ FADC250_SLOTS 9 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3384 3379 3372 3367 3361 3399 3364 3357 3378 3367 3383 3379 3373 3349 3381 3353 FADC250_PED 10 ############################ FADC250_SLOTS 10 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3382 3394 3375 3382 3381 3416 3371 3379 3371 3373 3360 3367 3406 3377 3353 3387 FADC250_PED 10 ############################ FADC250_SLOTS 13 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3348 3365 3384 3354 3378 3375 3359 3385 3373 3366 3381 3374 3359 3367 3347 3355 FADC250_PED 10 ############################ FADC250_SLOTS 14 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3362 3348 3353 3334 3364 3345 3360 3369 3364 3360 3327 3348 3348 3336 3353 3352 FADC250_PED 10 ############################ FADC250_SLOTS 15 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3345 3393 3385 3351 3380 3392 3381 3376 3365 3362 3366 3339 3364 3369 3344 3380 FADC250_PED 10 ############################ FADC250_SLOTS 16 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3372 3343 3362 3356 3355 3355 3342 3374 3350 3376 3342 3389 3370 3358 3369 3351 FADC250_PED 10 ############################ FADC250_SLOTS 17 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3348 3373 3368 3371 3359 3358 3365 3372 3348 3359 3372 3368 3374 3389 3360 3352 FADC250_PED 10 ############################ FADC250_SLOTS 18 ######################### FADC250_F_REV 0x0219 FADC250_B_REV 0x0908 FADC250_TYPE 0xfadc FADC250_MODE 1 FADC250_W_OFFSET 100 FADC250_W_WIDTH 50 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_ADC_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # channel: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FADC250_TET 10 FADC250_ALLCH_DAC 3369 3381 3359 3352 3363 3346 3376 3360 3379 3366 3361 3382 3354 3383 3345 3377 FADC250_PED 10