The sync latency of 0x50 is: 0xb600b60f tiSetAdr32: A32 Base address set to 0x08000000 TI CrateID register set to 51  Run with the TS. Optical port 1 is used tiSetSyncDelayWidth: Setting Sync delay = 336 (ns) width = 4064 (ns)  F1 TDC Download Initialized TDC 0 Slot # 3 at VME (Local) address 0x180000 (0xa4397000) Initialized TDC 1 Slot # 4 at VME (Local) address 0x200000 (0xa4417000) Initialized TDC 2 Slot # 5 at VME (Local) address 0x280000 (0xa4497000) Initialized TDC 3 Slot # 6 at VME (Local) address 0x300000 (0xa4517000) Initialized TDC 4 Slot # 7 at VME (Local) address 0x380000 (0xa4597000) Initialized TDC 5 Slot # 8 at VME (Local) address 0x400000 (0xa4617000) Initialized TDC 6 Slot # 9 at VME (Local) address 0x480000 (0xa4697000) Initialized TDC 7 Slot #10 at VME (Local) address 0x500000 (0xa4717000) jlabgefMemProbe: Clearing VME BERR/2eST (0x800cf900) at VME address 0x580000 f1Init: ERROR: No addressable board at VME (Local) addr=0xa4797000 (0xa4797000) jlabgefMemProbe: Clearing VME BERR/2eST (0x800cf900) at VME address 0x600000 f1Init: ERROR: No addressable board at VME (Local) addr=0xa4817000 (0xa4817000) Initialized TDC 10 Slot #13 at VME (Local) address 0x680000 (0xa4897000) Initialized TDC 11 Slot #14 at VME (Local) address 0x700000 (0xa4917000) Initialized TDC 12 Slot #15 at VME (Local) address 0x780000 (0xa4997000) Initialized TDC 13 Slot #16 at VME (Local) address 0x800000 (0xa4a17000) Initialized TDC 14 Slot #17 at VME (Local) address 0x880000 (0xa4a97000) jlabgefMemProbe: Clearing VME BERR/2eST (0x800cf900) at VME address 0x900000 f1Init: ERROR: No addressable board at VME (Local) addr=0xa4b17000 (0xa4b17000) jlabgefMemProbe: Clearing VME BERR/2eST (0x800cf900) at VME address 0x980000 f1Init: ERROR: No addressable board at VME (Local) addr=0xa4b97000 (0xa4b97000) jlabgefMemProbe: Clearing VME BERR/2eST (0x800cf900) at VME address 0xa00000 f1Init: ERROR: No addressable board at VME (Local) addr=0xa4c17000 (0xa4c17000) f1Init: Enabling f1TDC for VXS Clock and VXS Triggers (VXS Sync Reset) f1Init: Using configuration 1. f1Init: Unable to initialize all (18) TDC Modules f1Init: 13 TDC(s) successfully initialized  Number of F1TDCs initialized 13 sdInit: INFO: Initialization without respecting Library-Firmware version sdInit: SD (version 0xa5) initialized at Local Base address 0xa4cd7000 STATUS for SD at TI (Local) base address 0x00040000 (0xa4cd7000) -------------------------------------------------------------------------------- Firmware version = 0xa5 System Register = 0x80cc Status Register = 0x0410 CSR Test Reg = 0x0004 TI Fast Link ACTIVE Clock settings: A: PLL set for 250.00 MHz B: PLL set for 250.00 MHz Detected Clock: A: UNKNOWN B: 31.25 MHz Clock STATUS: A: Normal B: Normal Payload Boards Mask = 0x57ff Token Passing Boards Mask = 0x57ff BusyOut Boards Mask = 0x57ff TrigOut Boards Mask = 0x57ff VME Slots Enabled: 3 4 5 6 7 8 9 10 13 14 15 16 17 Token VME Slots Enabled: 3 4 5 6 7 8 9 10 13 14 15 16 17 BusyOut VME Slots Enabled: 3 4 5 6 7 8 9 10 13 14 15 16 17 Trigout VME Slots Enabled: 3 4 5 6 7 8 9 10 13 14 15 16 17 Busyout State Mask = 0x0000 TrigOut State Mask = 0x0000 VME Slots Busy Status High: VME Slots TrigOut Status High : --------------------------------------------------------------------------------  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=3 b_size=0.1120 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 225.9967 clk_period = 32.00 refcnt = 225 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.1118 full_range (ns) = 7327.9 tframe (ns) = 7264.0  Global Trigger Delay = 0.000000 (ns). Latency = 1400.000000  f1tdc: clk=1 V=2 b_size=0.0560 L=1400.0 W=1100.0 full_range/clk_period - 3.0 = 111.4984 clk_period = 32.00 refcnt = 111 refclkdiv = 128 hsdiv = 241 bin_size (ns) = 0.0559 full_range (ns) = 3663.9 tframe (ns) = 3616.0 before 3: -0.000000 after 3: 0.111815 before 4: 0.000000 after 4: 0.111815 before 5: 0.000000 after 5: 0.111815 before 6: -0.000000 after 6: 0.111815 before 7: 0.000000 after 7: 0.111815 before 8: 0.000000 after 8: 0.111815 before 9: 0.000000 after 9: 0.111815 before 10: 0.000000 after 10: 0.111815 before 13: 0.000000 after 13: 0.111815 before 14: 0.000000 after 14: 0.111815 before 15: 0.000000 after 15: 0.111815 before 16: 0.000000 after 16: 0.111815 before 17: -0.000000 after 17: 0.055907 f1TDC Module Configuration Summary Firmware ..................Addresses................. Slot Rev A24 A32 A32 Multiblock Range -------------------------------------------------------------------------------- 3 0x17 0x180000 0x09000000 0x10000000-0x11000000 4 0x17 0x200000 0x09800000 0x10000000-0x11000000 5 0x17 0x280000 0x0a000000 0x10000000-0x11000000 6 0x17 0x300000 0x0a800000 0x10000000-0x11000000 7 0x17 0x380000 0x0b000000 0x10000000-0x11000000 8 0x17 0x400000 0x0b800000 0x10000000-0x11000000 9 0x17 0x480000 0x0c000000 0x10000000-0x11000000 10 0x17 0x500000 0x0c800000 0x10000000-0x11000000 13 0x17 0x680000 0x0d000000 0x10000000-0x11000000 14 0x17 0x700000 0x0d800000 0x10000000-0x11000000 15 0x17 0x780000 0x0e000000 0x10000000-0x11000000 16 0x17 0x800000 0x0e800000 0x10000000-0x11000000 17 0x10 0x880000 0x0f000000 0x10000000-0x11000000 -------------------------------------------------------------------------------- Block .Signal Sources.. ....Channel.... Slot Level Clk Trig Sync MBlk Token BERR Enabled Mask -------------------------------------------------------------------------------- 3 1 FP SOFT SOFT YES VXS-F NO 0xFFFFFFFF 4 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 5 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 6 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 7 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 8 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 9 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 10 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 13 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 14 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 15 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 16 1 FP SOFT SOFT YES VXS NO 0xFFFFFFFF 17 1 FP SOFT SOFT YES VXS-L YES 0xFFFFFFFF -------------------------------------------------------------------------------- f1TDC Chip Configuration Bin Full Rollover Slot Chip Rez PL PTW Size Range Count -------------------------------------------------------------------------------- 3 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 4 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 5 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 6 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 7 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 8 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 9 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 10 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 13 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 14 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 15 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 16 ALL Norm 1100.0 1400.0 0.1118 7327.9 64964 17 ALL High 1100.0 1400.0 0.0559 3663.9 64678 --------------------------------------------------------------------------------