/*************************************************************************
 *
 *  ti_slave_list.c - Library of routines for readout and buffering of 
 *                    events using a JLAB Trigger Interface V3 (TI) with 
 *                    a Linux VME controller in CODA 3.0.
 * 
 *                    This is for a TI in Slave Mode controlled by a
 *                    Master TI or Trigger Supervisor
 *
 *        Modified:  Tue Apr 29 09:57:23 EDT 2014  B. Zihlmann
 *                   adaped for CDC readout using TS
 *
 */

/* Event Buffer definitions */
#define MAX_EVENT_POOL     10
#define MAX_EVENT_LENGTH   4096*1000   /* Size in Bytes: can not be more than 4MB*/


/* Define TI Type (TI_MASTER or TI_SLAVE) */
#define TI_SLAVE
/* TS Fiber Link trigger source (from TI Master, TD, or TS), POLL for available data */
#define TI_READOUT TI_READOUT_TS_POLL 
/* TI VME address, or 0 for Auto Initialize (search for TI by slot) */
#define TI_ADDR (21<<19)            

/* Measured longest fiber length in system */
/*#define FIBER_LATENCY_OFFSET 0x3A */
#define FIBER_LATENCY_OFFSET 0xCA

#define BLOCKLEVEL 1
#define BUFFERLEVEL 1
/*int blockLevel = BLOCKLEVEL;*/

/*int tsCrate=0;*/

#include "dmaBankTools.h"   /* Macros for handling CODA banks */
#include "tiprimary_list.c" /* Source required for CODA readout lists using the TI */

#include "f1tdcLib.h"
extern int f1AddrList[F1_MAX_BOARDS]; 
extern int f1tdcA32Base;  

#include "ccdb_inc.h" /* include file for C++ API wrapper*/

/* private variables for the time being needed for hard coded stuff*/
int  HOSTROC = 0;
char hnam[128];
char str1[128];
char DETECTOR[128];
int NTDCS = 0;
int SLOT = 3;
int NODAC = 1; /* if set to 1 set all DAC valvues to 0x8000 */ 
int ERRORCounter = 0;
int ERRORLOG = 100;

/* CCDB DATABASE VARIABLES*/
int DAC_Values[20][72];
int Thresholds[20][72];
int FA125ReadOutMode;
int FA125Latency;
int FA125WindowSize;
int FA125NSB;
int FA125NSA;
int FA125NP;


int EventCounter = 0;


/****************************************
 *  DOWNLOAD
 ****************************************/
void
rocDownload()
{
  int stat;
  int iFlag;
  int offset = 0;
  int k = 0;

  f1tdcA32Base = 0x09000000;


  /* hard code numbers here for the time being*/
  /* and code that I understand */
  /* CONFIGURATION PARAMETERS FOR THE CRATE AND THE ADCS ARE CURRENTLY TAKEN FROM */
  /* ONLINE_CCDB AS DAQ CONFIGURATiON SCHEEME IS STILL UNDER CONTRUCTION */
  gethostname(hnam,128);
  strncpy(str1, &hnam[6], 128);
  HOSTROC = atoi(str1);
  strncpy(DETECTOR,&hnam[3],3);
  DETECTOR[3] = '\0';

  NTDCS = GetCrateConfigfromdatabase(HOSTROC, DETECTOR);
  printf("Number of TDCs: %d\n",NTDCS);
  if (NTDCS<1)
    {
      printf("rocDownload ERROR: %s ROC %d    failed to read configuration from database!", DETECTOR, HOSTROC);
    }
  else
    {
      printf("rocDownload: %s ROC %d: configure for %d TDCs !", DETECTOR, HOSTROC, NTDCS);
    }

  /* Setup Address and data modes for DMA transfers
   *   
   *  vmeDmaConfig(addrType, dataType, sstMode);
   *
   *  addrType = 0 (A16)    1 (A24)    2 (A32)
   *  dataType = 0 (D16)    1 (D32)    2 (BLK32) 3 (MBLK) 4 (2eVME) 5 (2eSST)
   *  sstMode  = 0 (SST160) 1 (SST267) 2 (SST320)
   */

  vmeDmaConfig(2,5,1); 

  /* Define BLock Level variable to a default */
  /* will be set by TS */
  blockLevel = 1;


  /*****************
   *   TI SETUP
   *****************/

  /* Set the sync delay width to 0x40*32 = 2.048us */
  tiSetSyncDelayWidth(0x54, 0x40, 1);

  /* Set Trigger Buffer Level */
  tiSetBlockBufferLevel(BUFFERLEVEL);


  printf("rocDownload: Initialize TDCs\n");
  offset = 0;
  for (k=0; k<NTDCS; k++) {
    int slot = k + SLOT + offset;
    if (slot==10) {
      offset = 2;
    }
    f1AddrList[k] = slot<<19;    
  }
  
  iFlag  = (1<<17); /* use f1AddrList */
  /*
    bits 2-1:  defines Trigger source
    (0) 0 0  VXS (P0)
    (1) 0 1  Internal Timer
    (2) 1 0  Internal Multiplicity Sum
    (3) 1 1  P2 Connector (Backplane)
    bit    3:  NOT USED WITH THIS FIRMWARE VERSION
    bits 5-4:  defines Clock Source
    (0) 0 0  P2 Connector (Backplane)
    (1) 0 1  VXS (P0)
    (2) 1 0  Internal 125MHz Clock
  */
  
  iFlag |= F1_TRIGSRC_VXS;  /* Trigger Source */
  iFlag |= F1_CLKSRC_VXS;  /* Clock Source */
  iFlag |= F1_SRSRC_VXS; /* sync source*/
    
  /* V3 (SLOW) + V2 (FAST) */
  f1ConfigReadFile("/home/hdcdcops/DAQ/daq_dev_vers/daq/config/cdc/newf1config_lat1400_win1300.dat");
  stat = f1Init(f1AddrList[0], 0, NTDCS, iFlag);
  if (stat != OK) 
    {
      printf("rocDownload ERROR: %s ROC %d   f1Init failed, stop right here!!!", DETECTOR, HOSTROC);
      return -1;
    }
 
  f1GStatus(0);
  f1GEnableBusError();
  f1EnableMultiBlock(1);

  /* Init the SD library so we can get status info */
  stat = sdInit();
  if(stat==0) 
    {
      sdSetActiveVmeSlots(f1ScanMask());
    }
  sdStatus(0);	
  tiStatus(0);

  printf("rocDownload: User Download Executed\n");

  printf("\n");
  printf("rocDownload: TI FIBER LATENCY MEASUREMENT  DOWNLOAD %d \n",tiGetFiberLatencyMeasurement());
  printf("\n");

}

/****************************************
 *  PRESTART
 ****************************************/
void
rocPrestart()
{
  unsigned short iflag;
  int stat;
  int islot;

  /* Unlock the VME Mutex */
  vmeBusUnlock();

  tiStatus(0);
  
  printf("\n");
  printf(" TI FIBER LATENCY MEASUREMENT  PRESTART %d \n",tiGetFiberLatencyMeasurement());
  printf("\n");


  printf("rocPrestart: %s ROC %d User Prestart Executed\n", DETECTOR, HOSTROC);

}

/****************************************
 *  GO
 ****************************************/
void
rocGo()
{
  int islot;

  f1ResetToken(f1Slot(0));

  f1GEnableData(0);
  f1GEnable();
 
  /* Get the broadcasted Block Level from TS or TI Master */
  blockLevel = tiGetCurrentBlockLevel();
  printf("rocGo: Block Level set to %d\n",blockLevel);

  /* Enable/Set Block Level on modules, if needed, here */
  f1GSetBlockLevel(blockLevel);
  
  printf("\n");
  printf("rocGo: TI FIBER LATENCY MEASUREMENT  GO %d \n",tiGetFiberLatencyMeasurement());
  printf("\n");


}

/****************************************
 *  END
 ****************************************/
void
rocEnd()
{
  int islot;

  f1GStatus(0);
  f1GDisable();

  tiStatus(0);

  printf("rocEnd: %s ROC %d Ended after %d blocks\n", DETECTOR, HOSTROC, tiGetIntCount());
  EventCounter = 0;
}

/****************************************
 *  TRIGGER
 ****************************************/
/*void rocTrigger()*/
rocTrigger(int arg)
{
  int ii, islot;
  int stat, dCnt, len=0, idata;
  unsigned int val;
  unsigned int *start;
  int timeout = 100000;
  int iread, gbready;

  EventCounter++;
  printf("Event Number: %d\n",EventCounter);

  /* Set TI output 1 high for diagnostics */
  /*tiSetOutputPort(1,0,0,0);*/
  
  dCnt = tiReadTriggerBlock(dma_dabufp);
  if(dCnt<=0)
    {
      printf("tiReadBlock(): %s ROC %d No data or error.  dCnt = %d\n",DETECTOR, HOSTROC, dCnt);
      daLogMsg("ERROR","tiReadTriggerBlock(): %s ROC %d No data or error.  dCnt = %d\n", DETECTOR, HOSTROC, dCnt);
    }
  else
    {
      dma_dabufp += dCnt;
    }

  /* TDC data with bank type=6 to indicat jlab module data */

  for(iread = 0; iread < timeout; iread++) {
      gbready = f1GBready();
      if(gbready == f1ScanMask()){
	break;
      }
  }
  if(iread==timeout) {
    printf("f1 (%d) timeout  (f1GBready: 0x%08x != 0x%08x)\n",iread, gbready, f1ScanMask());
    daLogMsg("ERROR","fa125 timeout  (fa125GBready: 0x%08x != 0x%08x) on Event %d\n",gbready,f1ScanMask(),EventCounter);
  } else  {
    BANKOPEN(16,BT_UI4,0);
    dCnt = f1ReadBlock(0,(volatile UINT32 *)dma_dabufp,0x4000,2);
    if(dCnt<=0) {
      printf("rocTrigger(): %s ROC %d   No f1TDC data or error.  dCnt = %d\n", DETECTOR, HOSTROC, dCnt);
      daLogMsg("ERROR","rocTrigger(): %s ROC %d   No f1TDC data or error.  dCnt = %d\n", DETECTOR, HOSTROC, dCnt);
    } else {
      dma_dabufp += dCnt;
    }
    BANKCLOSE;
  }
  
  f1ResetToken(f1Slot(0));

  /* Set TI output 0 low */
  tiSetOutputPort(0,0,0,0);

}

void
rocCleanup()
{
  int islot=0;

  printf("rocCleanup: %s ROC %d   : %s: Reset all Modules\n", DETECTOR, HOSTROC, __FUNCTION__);
  
}